The present invention relates to semiconductor wafer fabrication, and more specifically, to methods and structures for controlling semiconductor wafer stress and topography with backside patterning.
In the field of semiconductor wafer fabrication, structures deposited on a wafer impart stress onto the surrounding substrate. As industry demands increase for lighter and thinner semiconductor wafers, semiconductors are more susceptible to relatively significant distortions in wafer topography upon application of such stressors. As critical dimensions continue to decrease, issues such as topography and overlay errors become more significant in semiconductor wafer manufacturing. For example, collections of embedded dynamic random-access memory (eDRAM) structures can locally distort semiconductor wafers both in and out of plane such that a collective effect of wafer stress results in a topography variation on the scale of 100 nanometers. Distorted wafers can interfere with downstream processes, such as chemical mechanical planarization (CMP) or subsequent lithography steps, and can result in systematic with-die variability and yield loss.